----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:58:26 10/08/2013 
-- Design Name: 
-- Module Name:    full_cla_adder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity full_cla_adder is
    Port ( a : in  STD_LOGIC_VECTOR (31 downto 0);
           b : in  STD_LOGIC_VECTOR (31 downto 0);
           cin : in  STD_LOGIC;
           sub : in  STD_LOGIC_VECTOR (1 downto 0);
           sum : out  STD_LOGIC_VECTOR (31 downto 0);
           cout : out  STD_LOGIC);
end full_cla_adder;

architecture Behavioral of full_cla_adder is

component cla_8bit
    Port ( a	: in	STD_LOGIC_VECTOR (7 downto 0);
			  b	: in	STD_LOGIC_VECTOR (7 downto 0);
			  cin : in  STD_LOGIC;
           cout : out  STD_LOGIC;
           sum : out  STD_LOGIC_VECTOR (7 downto 0));
end component;

component mux
    Port ( ctrl : in  STD_LOGIC_VECTOR (1 downto 0);
           output : out  STD_LOGIC;
           in0 : in  STD_LOGIC;
           in1 : in  STD_LOGIC;
           in2 : in  STD_LOGIC;
           in3 : in  STD_LOGIC);
end component;

signal not_b: std_logic_vector(31 downto 0);
signal mux_output: std_logic_vector(31 downto 0);
signal c1,c2,c3: std_logic;
signal sumcla0, sumcla1, sumcla2, sumcla3
			,cla_input_a0, cla_input_a1, cla_input_a2, cla_input_a3
			,cla_input_b0, cla_input_b1, cla_input_b2, cla_input_b3: std_logic_vector(7 downto 0);

begin

not_b(0) <= not b(0);
not_b(1) <= not b(1);
not_b(2) <= not b(2);
not_b(3) <= not b(3);
not_b(4) <= not b(4);
not_b(5) <= not b(5);
not_b(6) <= not b(6);
not_b(7) <= not b(7);
not_b(8) <= not b(8);
not_b(9) <= not b(9);
not_b(10) <= not b(10);
not_b(11) <= not b(11);
not_b(12) <= not b(12);
not_b(13) <= not b(13);
not_b(14) <= not b(14);
not_b(15) <= not b(15);
not_b(16) <= not b(16);
not_b(17) <= not b(17);
not_b(18) <= not b(18);
not_b(19) <= not b(19);
not_b(20) <= not b(20);
not_b(21) <= not b(21);
not_b(22) <= not b(22);
not_b(23) <= not b(23);
not_b(24) <= not b(24);
not_b(25) <= not b(25);
not_b(26) <= not b(26);
not_b(27) <= not b(27);
not_b(28) <= not b(28);
not_b(29) <= not b(29);
not_b(30) <= not b(30);
not_b(31) <= not b(31);

mux0: mux port map (sub, mux_output(0), b(0), not_b(0), 'X', 'X');
mux1: mux port map (sub, mux_output(1), b(1), not_b(1), 'X', 'X');
mux2: mux port map (sub, mux_output(2), b(2), not_b(2), 'X', 'X');
mux3: mux port map (sub, mux_output(3), b(3), not_b(3), 'X', 'X');
mux4: mux port map (sub, mux_output(4), b(4), not_b(4), 'X', 'X');
mux5: mux port map (sub, mux_output(5), b(5), not_b(5), 'X', 'X');
mux6: mux port map (sub, mux_output(6), b(6), not_b(6), 'X', 'X');
mux7: mux port map (sub, mux_output(7), b(7), not_b(7), 'X', 'X');
mux8: mux port map (sub, mux_output(8), b(8), not_b(8), 'X', 'X');
mux9: mux port map (sub, mux_output(9), b(9), not_b(9), 'X', 'X');
mux10: mux port map (sub, mux_output(10), b(10), not_b(10), 'X', 'X');
mux11: mux port map (sub, mux_output(11), b(11), not_b(11), 'X', 'X');
mux12: mux port map (sub, mux_output(12), b(12), not_b(12), 'X', 'X');
mux13: mux port map (sub, mux_output(13), b(13), not_b(13), 'X', 'X');
mux14: mux port map (sub, mux_output(14), b(14), not_b(14), 'X', 'X');
mux15: mux port map (sub, mux_output(15), b(15), not_b(15), 'X', 'X');
mux16: mux port map (sub, mux_output(16), b(16), not_b(16), 'X', 'X');
mux17: mux port map (sub, mux_output(17), b(17), not_b(17), 'X', 'X');
mux18: mux port map (sub, mux_output(18), b(18), not_b(18), 'X', 'X');
mux19: mux port map (sub, mux_output(19), b(19), not_b(19), 'X', 'X');
mux20: mux port map (sub, mux_output(20), b(20), not_b(20), 'X', 'X');
mux21: mux port map (sub, mux_output(21), b(21), not_b(21), 'X', 'X');
mux22: mux port map (sub, mux_output(22), b(22), not_b(22), 'X', 'X');
mux23: mux port map (sub, mux_output(23), b(23), not_b(23), 'X', 'X');
mux24: mux port map (sub, mux_output(24), b(24), not_b(24), 'X', 'X');
mux25: mux port map (sub, mux_output(25), b(25), not_b(25), 'X', 'X');
mux26: mux port map (sub, mux_output(26), b(26), not_b(26), 'X', 'X');
mux27: mux port map (sub, mux_output(27), b(27), not_b(27), 'X', 'X');
mux28: mux port map (sub, mux_output(28), b(28), not_b(28), 'X', 'X');
mux29: mux port map (sub, mux_output(29), b(29), not_b(29), 'X', 'X');
mux30: mux port map (sub, mux_output(30), b(30), not_b(30), 'X', 'X');
mux31: mux port map (sub, mux_output(31), b(31), not_b(31), 'X', 'X');

cla_input_a0 <= a(7)&a(6)&a(5)&a(4)&a(3)&a(2)&a(1)&a(0);
cla_input_b0 <= mux_output(7)&mux_output(6)&mux_output(5)&mux_output(4)
								&mux_output(3)&mux_output(2)&mux_output(1)&mux_output(0);
								
cla_input_a1 <= a(15)&a(14)&a(13)&a(12)&a(11)&a(10)&a(9)&a(8);
cla_input_b1 <= mux_output(15)&mux_output(14)&mux_output(13)&mux_output(12)
								&mux_output(11)&mux_output(10)&mux_output(9)&mux_output(8);

cla_input_a2 <= a(23)&a(22)&a(21)&a(20)&a(19)&a(18)&a(17)&a(16);
cla_input_b2 <= mux_output(23)&mux_output(22)&mux_output(21)&mux_output(20)
								&mux_output(19)&mux_output(18)&mux_output(17)&mux_output(16);
								
cla_input_a3 <= a(31)&a(30)&a(29)&a(28)&a(27)&a(26)&a(25)&a(24);
cla_input_b3 <= mux_output(31)&mux_output(30)&mux_output(29)&mux_output(28)
								&mux_output(27)&mux_output(26)&mux_output(25)&mux_output(24);


cla0: cla_8bit port map(cla_input_a0, cla_input_b0, cin, c1, sumcla0);
cla1: cla_8bit port map(cla_input_a1, cla_input_b1, c1, c2, sumcla1);
cla2: cla_8bit port map(cla_input_a2, cla_input_b2, c2, c3, sumcla2);
cla3: cla_8bit port map(cla_input_a3, cla_input_b3,c3, cout, sumcla3);

sum <= sumcla3&sumcla2&sumcla1&sumcla0;


end Behavioral;

